Isolated metal-oxide-semiconductor field-effect transistors (MOSFETs) differ from conventional MOSFETs in that isolated transistors include a voltage isolating layer between a substrate and a transistor well (backgate). An advantage of the isolated transistor is that different bias potentials may be applied to the substrate and the backgate simultaneously. For example, a common application of isolated transistors involves setting the substrate to Ground, e.g., 0 volts, while applying a supply voltage, e.g., −8 volts, to the backgate. The isolation layer electrically isolates devices situated within the same substrate. Transistors and other semiconductor devices may be formed on the same substrate and operated at different voltages without interfering with each other. FIG. 1 is a cross-sectional view of a conventional semiconductor device 10 including an isolated NMOS transistor, which includes an n-type source region 11, an n-type drain region 12 and a gate 13. The NMOS transistor is formed within a p-type backgate which includes a heavily doped p+ region 14 to which a bias voltage may be applied. An n-type isolation layer 16 separates the backgate from a substrate 17 which includes a heavily doped p+ region 18 to which a substrate bias voltage may be applied. A resistor Riso 19 couples the isolation layer 16 to an isolation voltage Viso. A substrate voltage VSS is applied to the region 18 while a supply voltage VL is applied to the source 11 and the backgate region 14. The transistor may be activated by applying a bias voltage Vgate to the gate 13. The drain 12 is connected to an output Vout.
Although isolated MOSFETs are intended to provide complete electrical isolation, in practice complete isolation cannot be achieved because of parasitic circuit elements. Under certain operating conditions, the parasitic elements contribute to electrostatic discharge (ESD) and/or latchup failure in the device. ESD and latchup cause many failures in integrated circuits (ICs) including ICs that utilize isolated MOSFETs. Because ESD and latchup are independent and often competing factors in IC design, improved ESD performance often results in a corresponding worsened latchup performance, and vice versa.